The D Latch (Quickstart Tutorial)
The D Latch is a logic circuit most steadily used for storing information in digital programs. It’s primarily based on the S-R latch, nevertheless it doesn’t have an “undefined” or “invalid” state drawback. On this tutorial, you’ll study the way it works, its fact desk, and easy methods to construct one with logic gates.
What’s a D Latch?
A D latch can retailer a bit worth, both 1 or 0. When its Allow pin is HIGH, the worth on the D pin shall be saved on the Q output. It builds upon the design of the S-R latch, with just a few added logic gates. You may see a D Latch circuit primarily based on the S-R latch constructed with NAND gates under:
The inverter on the enter makes positive the S and the R inputs are all the time opposites, to keep away from the invalid state of each being 1. The 2 NAND gates create a brand new enter, E (Allow), that allows you to management once you wish to change the output to no matter is on the D enter.
Which means that the output Q can solely change when the allow sign is 1. If it’s 0, the output is unaffected by any modifications on D.
You may also construct a D Latch with AND and NOR gates as follows:
The D Latch may also be used to introduce delay in timing circuits, as a buffer, or for sampling information at particular intervals.
What’s the Distinction Between Latch and Flip Flop?
The phrases latch and flip flop are typically incorrectly used as synonyms since each can retailer a bit (1 or 0) at their outputs.
Whereas a latch can change its output at any time so long as it’s enabled, a flip flop is an edge-triggered machine that wants a clock transition to vary its output.
To construct a D Flip Flop, you’ll want two D latches, like this:
How Does the D Latch Work?
Because the output Q solely modifications when the E enter is 1, you’ll get the next fact desk:
|1||0||0||Reset Q to 0|
|1||1||1||Set Q to 1|
Within the first row of the reality desk, the E enter is 0. Meaning the latch shouldn’t be enabled, so nothing occurs. The Q output retains no matter worth it had. It doesn’t matter what worth the D enter has, the Q output received’t change, it’s going to maintain its worth as it’s. That is how this circuit “remembers” a bit.
Check out the following two rows. Right here the E enter is 1, so the latch is enabled. Which means that if the D enter is 0, the Q output shall be reset to 0. If the D enter is 1, the Q output shall be set to 1.
Analyzing the Circuit
You may construct a D Latch circuit by including three logic gates to the S-R latch circuit. Within the subsequent picture, you possibly can see the D Latch circuit’s bit path when it’s enabled and it has 0 on the D enter.
To investigate the above circuit it’s good to keep in mind that the NAND gate solely produces a 0 when its two inputs are each 1. In all different circumstances, it offers a 1.
To start with, the inputs to the first NAND gate are 0 and 1, due to this fact, its output is 1. The 2nd NAND gate has each inputs at 1, so it returns 0.
The outputs of the first and 2nd NAND gates are the inputs to the part of the circuit that represents the essential S-R latch. With that in thoughts, you possibly can divide the bits into two teams: Those who got here earlier than the S-R latch (Purple) and people who had been produced by the S-R Latch (Inexperienced).
Lastly, should you have a look at the 4th NAND gate. You may see that one among its inputs is 0 because of the 2nd NAND gate. That data is sufficient to let you know that whatever the worth of its different enter, it’s going to give out 1. This bit is suggestions to one of many inputs of the third NAND gate. The opposite one is 1 because of the 1st NAND gate, so the results of the Q output is 0 – the identical as enter D.
Strive going by this when D is 1 as a substitute, and also you’ll see that the output turns into 1.
From this bit path, you possibly can conclude that the D Latch updates the output Q to what’s on the D enter so long as the E enter is 1.
Experiment: Construct Your Personal D Latch Circuit
As a sensible instance, you possibly can construct a primary D Latch circuit utilizing logic gates and check it out with pushbuttons. R1 and R2 are pull-down resistors to verify the inputs are 0 when the buttons are usually not pushed:
As you possibly can see in part 1 of the picture, Q is 0 (LED L1 off), and each PB1 and PB2 are usually not pressed.
Subsequent, have a look at part 2 the place PB2 is pushed. You now have a 1 on the D enter, however the output Q stays as 0 as a result of the E enter hasn’t acquired an allow sign but.
Part 3 exhibits how PB1 is pressed, so a 1 on the E enter seems and locations the bit 1 from D to Q. When Q is 1 it activates LED L1.
When PB1 and PB2 return to their unique states in part 4, LED L1 stays ON indicating that the Q output has not modified.
To alter the output Q you would wish to push PB1 once more.
To assemble the above circuit you want:
- 4 NAND gates (Ex CD4011)
- One NOT gate (Ex CD4049 or CD4069)
- 2x pushbuttons
- 1x LED
- 2x 10 kΩ resistors (R1 and R2)
- 1x 330 Ω resistors (R3)
Do you’ve got any questions concerning the D Latch and the way it works? Let me know within the feedback under.