The JK Flip Flop (Quickstart Tutorial)

The JK Flip Flop is a kind of flip flop that may be set, reset, and toggled. It may be used for making counters, occasion detectors, frequency dividers, and way more.

On this tutorial, you’ll be taught the way it works, its fact desk, and tips on how to construct one with logic gates.

JK Flip Flop symbol
JK Flip Flop image

What’s a JK Flip Flop?

Flip flops are parts that may retailer a digital worth on their output. They’ve a Clock enter (Clk) which determines after they can change the state of their output.

Opposite to what you’d assume, the 2 inputs of the JK Flip Flop, “J” and “Okay”, will not be abbreviations for what the pins do (which is the case for the S-R latch). They had been chosen by its inventor Jack Kilby (JK) to differentiate his flip flop design from different varieties.

You’ll be able to see a primary implementation of the circuit under. It’s based mostly on the S-R latch and constructed with NAND gates:

Jk Flip Flop basic NAND cirucuit
JK Flip Flop primary circuit

The J and Okay inputs of the JK flip flop can be utilized to set, reset, or toggle the output, like this:

  • J=1 and Okay=0 units the output to 1
  • J=0 and Okay=1 resets the output to 0
  • J=1 and Okay=1 toggles the output

However for the flip flop to make any change, its Clock enter have to be 1. Take a look at the reality desk under:

Clk J Okay Q Description
 0 X X Q Clk in 0 no
change in Q
1 0 0 Q Reminiscence
(no change)
1 1 0 1 Set
 1 0 1 0 Reset
 1 1 1 Toggle
JK Flip Flop Fact Desk

Another technique to implement the fundamental JK flip flop circuit is utilizing two AND gates and two NOR gates as follows (it really works precisely just like the one constructed with NAND gates):

JK Circuit with AND and NOR gates

Racing Drawback

In precept, the fundamental implementation above works, however a timing drawback arises.  When the clock is “1” and also you wish to toggle the output, it should toggle actually quick between “1” and “0” till the clock goes again to “0”. This concern is named a race situation.

You’ll be able to remedy this by making the the flip flop pulse-triggered or edge-triggered.

Pulse-Triggered JK Flip Flop

Under you may have a pulse-triggered JK flip flop based mostly on the Grasp-Slave precept:

Master-Slave JK Flip Flop
Grasp-Slave circuit

As you possibly can see, to construct this configuration you want a primary JK Flip Flop circuit tied along with an S-R flip flop.

To know how this model works try its timing diagram under:

Timing diagram for the master-slave setup

As quickly because the clock makes a rising edge ↑, which is a change from 0 to 1 (0→1), it triggers the grasp part. Because of this, the worth of the outputs on this part adjustments. These alerts are related to the slave part, however this doesn’t set off on the rising edge as a result of the clock has been inverted.

As soon as the clock sign produces a falling edge ↓, a change from 1 to 0 (1→0), it triggers the slave part, inflicting the Q output to replicate the grasp’s output worth.

So this circuit requires a whole pulse (0→1 →0) with a purpose to change the output. That’s why this configuration is named pulse-triggered JK Flip Flop.

Clk J Okay Q Description
 0 or 1 X X Q No pulse
no change
0→1 →0 0 0 Q Reminiscence
(no change)
0→1 →0 1 0 1 Set
0→1 →0 0 1 0 Reset
0→1 →0 1 1 Toogle
Fact Desk

Edge-Triggered JK Flip Flop

Not like the Grasp-Slave design, you possibly can set off this edge-triggered JK Flip Flop simply with both a rising edge ↑ or a falling edge ↓.

Under you may have the timing diagram for one which triggers on the rising edge:

Edge-triggered timing diagram

The above image exhibits how this circuit simply wants a rising edge on the Clk enter to vary the state of the output Q. And it’ll solely change on the rising edge.

Clk J Okay Q Description
 0 or 1 X X Q No rising edge
no change
0→1 (↑) 0 0 Q Reminiscence
(no change)
 0→1 (↑) 1 0 1 Set
 0→1 (↑) 0 1 0 Reset
 0→1 (↑) 1 1 Toogle
Edge-triggered JK Flip Flop Fact Desk

To construct a JK Flip Flop that triggers solely with rising edge alerts, you need to use a rising edge-triggered D flip flop, a NOT gate, and NAND gates as follows:

Edge-triggered JK Flip Flop circuit
Edge-triggered JK Flip Flop circuit


Do you may have any questions on how any such flip flop works? Let me know within the feedback under.

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