TSMC lays out a killer roadmap

At present N3, which entered quantity manufacturing in This autumn 2022, is essentially the most superior course of.

Following it up is N3E which has handed expertise qualification and achieved its efficiency and yield targets. It has obtained the primary wave of buyer product tape-outs and can begin quantity manufacturing within the second half of 2023.

The variety of new tape–outs for N3E is 1.5 to 2X that of N5 over the identical interval.

Developing are:

N3P, which provides further efficiency and space advantages whereas preserving design rule compatibility with N3E to maximise IP re-use. It’s scheduled to enter manufacturing within the second half of 2024 It is going to ship 5% extra pace on the similar leakage, 5% to 10% energy discount on the similar pace, and 1.04X extra chip density in contrast with N3E.

N3X, which is tuned for HPC purposes, gives further Fmax achieve to spice up overdrive efficiency at a modest  trade-off with leakage. This interprets to five% extra pace versus  N3P at drive voltage of 1.2V, with the identical improved  chip density as N3P. N3X will enter quantity manufacturing in 2025.

N3AE, which is the  trade’s first Auto Early expertise on 3nm, provides automotive PDKs based mostly on N3E and permits clients to launch designs on the 3nm node for automotive purposes, main  a completely automotive–certified N3A course of in 2025.

N2, which is predicated on the GAA nanosheet transistor, for which quantity manufacturing is focused for 2025; N2P and N2X are deliberate for 2026.

The efficiency of the nanosheet transistor has exceeded 80% of the corporate’s expertise targets whereas demonstrating glorious energy, effectivity and decrease Vmin, says TSMC, which is nice for power–environment friendly computing.

TSMC has exercised N2 design collateral within the bodily implementation of an Arm A715 CPU core to measure PPA enchancment: it achieved a 30% pace achieve on the similar energy, or 33% energy discount on the similar pace at round 0.9V, in comparison with the N3E, high-density, 2-to-1, fin normal cell.

A part of the TSMC expertise platform – a bottom energy rail – gives an extra pace and density increase on high of the baseline expertise

The bottom energy rail is finest suited to HPC merchandise and shall be accessible within the second half of 2025.

The expertise improves pace by greater than 10-12% from decreasing IR drop and sign RC delays and reduces the frontside space required for logic by 10-15%.


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